Skip to content Skip to sidebar Skip to footer


« Back to Glossary Index

In DRAMs and SRAMs, a method for increasing the performance using multistage circuitry to stack or save data while new data is being accessed. The depth of a pipeline varies from product to product. For example, in an EDO DRAM, one bit of data appears on the output while the next bit is being accessed. In some SRAMs, pipelines may contain bits of data or more.